Non-volatile semiconductor memory devices, which are not only electrically writable and deletable but also capable of keeping stored data even if the power supply is cut off, have become a mainstream of memories in the memory market. The technological advance of such memories has been greatly attributable to the miniaturization of semiconductor integrated circuits. The miniaturization of semiconductor integrated circuits relies on the photolithography technique, especially. The photolithography technique is implemented using an exposure apparatus to expose a photoresist applied on a semiconductor wafer to a desired pattern of light projected, and also using a mask for exposure, which is called a reticle, with a microscopic pattern. A pattern of contact holes is one of the difficult patterns for the photolithography technique. A non-volatile semiconductor memory device includes a memory cell transistor as a principal constituent element, and microscopic diffusion layers, called a drain region and a source region, are formed in the memory cell transistor, The wiring in the upper layer needs to form contacts with the microscopic diffusion layers through either contact plugs or local interconnects formed in the interlayer insulation layer. Each contact with the drain region (drain diffusion layer) must be formed with certainty on the microscopic diffusion layer to prevent short circuit to the adjacent bit. A source potential is applied from the metal wiring in the upper layer to the local interconnect through the via contacts shunting for each memory cell array, and is then applied from the local interconnect to the source diffusion layers of the respective memory cells.
In the case of conventional non-volatile semiconductor memory devices, however, there is a problem that via-contact holes for supplying the source potential are patterned in units of memory cell arrays, which in turn causes disruption of the cyclic pattern of memory cells. Specifically, when the via-contact holes for drain and the via-contact holes for supplying the source potential are lithographed with a single reticle, the process margin is decreased significantly.
Accordingly, in the conventional non-volatile semiconductor memory devices, each shunt region is formed to have a width equivalent to two pitches of the memory cells to minimize the disruption of the cyclic pattern of memory cells. In this way, both of the patterning of the via-contact holes for drain and the patterning of the via-contact holes for supplying the source potential are stabilized. However, it is basically desirable that the width assigned to each shunt region be as small as a single pitch of the memory cells. Assigning a two-pitch width to each shunt region poses a problem of directly increasing the total area of the chip. For example, having a hundred shunt regions, a chip has an area penalty, as a whole, that is one hundred times larger than the area penalty for each single shunt region.